Sciweavers

11061 search results - page 1811 / 2213
» Computer Architecture
Sort
View
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
16 years 7 months ago
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve lowpower dissipation and h...
Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Ku...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 7 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
VLSID
2001
IEEE
132views VLSI» more  VLSID 2001»
16 years 7 months ago
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
This paper presents novel techniques for the cycle-accurate power macro-modeling of complex RTL components. The proposed techniques are based on the observation that RTL component...
Nachiketh R. Potlapally, Michael S. Hsiao, Anand R...
OSDI
2004
ACM
16 years 7 months ago
Program-Counter-Based Pattern Classification in Buffer Caching
Program-counter-based (PC-based) prediction techniques have been shown to be highly effective and are widely used in computer architecture design. In this paper, we explore the op...
Chris Gniady, Ali Raza Butt, Y. Charlie Hu
ISPASS
2010
IEEE
16 years 1 months ago
Hardware prediction of OS run-length for fine-grained resource customization
—In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors...
David Nellans, Kshitij Sudan, Rajeev Balasubramoni...
« Prev « First page 1811 / 2213 Last » Next »