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VLSID
2005
IEEE
224views VLSI» more  VLSID 2005»
16 years 7 months ago
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
VLSID
2004
IEEE
114views VLSI» more  VLSID 2004»
16 years 7 months ago
High-Speed Optoelectronics Receivers in SiGe
This paper focuses on the investigation of integrated CMOS and Silicon/Germanium (SiGe) devices for highspeed optical receiver circuits. In this paper, we present several competit...
Amit Gupta, Steven P. Levitan, Leo Selavo, Donald ...
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
16 years 7 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski
VLSID
2004
IEEE
212views VLSI» more  VLSID 2004»
16 years 7 months ago
On Design and Implementation of an Embedded Automatic Speech Recognition System
We present a new design of an Embedded Speech Recognition System. It combines the aspects of both hardware and software design to implement a speaker dependent, isolated word, sma...
Sujay Phadke, Rhishikesh Limaye, Siddharth Verma, ...
160
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VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
16 years 7 months ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang
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