The proliferation of the Internet has a ected the business model of almost all semiconductor and VLSI CAD companies that rely on intellectual property (IP) as their main source of...
Darko Kirovski, David T. Liu, Jennifer L. Wong, Mi...
We have developed a function-level power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build th...
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag ...
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...