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176
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HPCA
2007
IEEE
16 years 7 months ago
2007
IEEE
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
166
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HPCA
2007
IEEE
16 years 7 months ago
2007
IEEE
Caches are organized at a line-size granularity to exploit spatial locality. However, when spatial locality is low, many words in the cache line are not used. Unused words occupy ...
201
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HPCA
2007
IEEE
16 years 7 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
218
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HPCA
2007
IEEE
16 years 7 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
255
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...