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186
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VLSID
2005
IEEE
128views VLSI» more  VLSID 2005»
16 years 7 months ago
On-Line Synthesis for Partially Reconfigurable FPGAs
An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-l...
Renqiu Huang, Ranga Vemuri
208
Voted
VLSID
2004
IEEE
120views VLSI» more  VLSID 2004»
16 years 7 months ago
Dynamic Power Optimization of Interactive Systems
Abstract-- Power has become a major concern for mobile computing systems such as laptops and handhelds, on which a significant fraction of software usage is interactive instead of ...
Lin Zhong, Niraj K. Jha
194
Voted
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
16 years 7 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
189
Voted
VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
16 years 7 months ago
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks
Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In [1], we proposed a new switching probability model based on Bayesian N...
Sanjukta Bhanja, N. Ranganathan
VLSID
2002
IEEE
120views VLSI» more  VLSID 2002»
16 years 7 months ago
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...
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