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MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
15 years 7 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
APIN
1999
107views more  APIN 1999»
15 years 7 months ago
Massively Parallel Probabilistic Reasoning with Boltzmann Machines
We present a method for mapping a given Bayesian network to a Boltzmann machine architecture, in the sense that the the updating process of the resulting Boltzmann machine model pr...
Petri Myllymäki
JIIS
2002
141views more  JIIS 2002»
15 years 7 months ago
Combining Approximation Techniques and Vector Quantization for Adaptable Similarity Search
Adaptable similarity queries based on quadratic form distance functions are widely popular in data mining application domains including multimedia, CAD, molecular biology or medica...
Christian Böhm, Hans-Peter Kriegel, Thomas Se...
ML
2002
ACM
114views Machine Learning» more  ML 2002»
15 years 7 months ago
Building a Basic Block Instruction Scheduler with Reinforcement Learning and Rollouts
The execution order of a block of computer instructions on a pipelined machine can make a difference in running time by a factor of two or more. Compilers use heuristic schedulers...
Amy McGovern, J. Eliot B. Moss, Andrew G. Barto
RTS
2002
106views more  RTS 2002»
15 years 7 months ago
Cello: A Disk Scheduling Framework for Next Generation Operating Systems
In this paper, we present the Cello disk scheduling framework for meeting the diverse service requirements of applications. Cello employs a two-level disk scheduling architecture,...
Prashant J. Shenoy, Harrick M. Vin
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