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VLSID
2003
IEEE
114views VLSI» more  VLSID 2003»
16 years 8 months ago
Substrate Bias Effect on Cycling Induced Performance Degradation of Flash EEPROMs
Cycling induced performance degradation of flash EEPROMs has been reported for VB=0 and VB<0 programming operation. Compared to VB=0, VB<0 programming shows lower interface ...
S. Mahapatra, S. Shukuri, Jeff Bude
VLSID
2003
IEEE
148views VLSI» more  VLSID 2003»
16 years 8 months ago
Extending Platform-Based Design to Network on Chip Systems
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
Juha-Pekka Soininen, Axel Jantsch, Martti Forsell,...
VLSID
2003
IEEE
108views VLSI» more  VLSID 2003»
16 years 8 months ago
A Low Power-Delay Product Page-Based Address Bus Coding Method
The working-zone encoding (WZE) method employing locality of memory reference was previously proposed to reduce address bus switching activity. This paper presents an encoding met...
Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin
VLSID
2002
IEEE
129views VLSI» more  VLSID 2002»
16 years 8 months ago
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylves...
VLSID
2002
IEEE
130views VLSI» more  VLSID 2002»
16 years 8 months ago
Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks
In preemptive real-time systems, a tighter estimate of the Worst Case Response Time(WCRT) of the tasks can be obtained if the layout of the tasks in memory is included in the esti...
Anupam Datta, Sidharth Choudhury, Anupam Basu
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