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VLSID
2005
IEEE
118views VLSI» more  VLSID 2005»
16 years 8 months ago
Battery Model for Embedded Systems
This paper explores the recovery and rate capacity effect for batteries used in embedded systems. It describes the prominent battery models with their advantages and drawbacks. It...
Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas ...
VLSID
2005
IEEE
121views VLSI» more  VLSID 2005»
16 years 8 months ago
Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications
In this paper, we have studied and compared the RF performance metrics, unity gain frequency (ft) and Noise Figure (NF), of the devices with channel engineering consisting of halo...
R. Srinivasan, Navakanta Bhat
173
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VLSID
2005
IEEE
98views VLSI» more  VLSID 2005»
16 years 8 months ago
False Path and Clock Scheduling Based Yield-Aware Gate Sizing
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
VLSID
2005
IEEE
132views VLSI» more  VLSID 2005»
16 years 8 months ago
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, ...
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
16 years 8 months ago
Bridge Over Troubled Wrappers: Automated Interface Synthesis
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
Vijay D'Silva, S. Ramesh, Arcot Sowmya
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