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160
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VLSID
2006
IEEE
16 years 8 months ago
2006
IEEE
In this paper, 16-bit, 50 MHz Current Steering DAC is designed. This DAC is implemented using TSMC 0.35 ?m technology. An optimum segmentation is done of 16-bits into binary and t...
222
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VLSID
2005
IEEE
16 years 8 months ago
2005
IEEE
In this article we address efficiency issues in implementation of Monte Carlo algorithm for 3D capacitance extraction. Error bounds in statistical capacitance estimation are discus...
173
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VLSID
2005
IEEE
16 years 8 months ago
2005
IEEE
: The direct result of shrinking devices is not only higher densities but also increased switching activity and thus higher device temperatures. The variation in temperature over t...
194
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VLSID
2005
IEEE
16 years 8 months ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
227
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VLSID
2005
IEEE
16 years 8 months ago
2005
IEEE
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...