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VLSID
2007
IEEE
152views VLSI» more  VLSID 2007»
16 years 7 months ago
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip K...
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
16 years 7 months ago
Evaluating Run-Time Techniques for Leakage Power Reduction
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishn...
FCCM
2009
IEEE
172views VLSI» more  FCCM 2009»
16 years 1 months ago
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization
Abstract—Precision analysis and optimization is very important when transforming a floating-point algorithm into fixedpoint hardware implementations. The core analysis techniqu...
Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu,...
ICC
2007
IEEE
153views Communications» more  ICC 2007»
16 years 1 months ago
An End-to-End Technique to Estimate the Transmission Rate of an IEEE 802.11 WLAN
— The deployment of wireless LANs (WLANs) has been steadily increasing over the years and estimating the actual bit rate of a WLAN device is important for management and applicat...
Antonio Augusto de Aragão Rocha, Rosa Maria...
CF
2004
ACM
16 years 9 days ago
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...