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VLSID
2008
IEEE
95views VLSI» more  VLSID 2008»
16 years 7 months ago
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor
In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long cha...
Biswajit Ray, Santanu Mahapatra
VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
16 years 7 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
VLSID
2004
IEEE
73views VLSI» more  VLSID 2004»
16 years 7 months ago
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
Reduction of worst-case delay and delay uncertainty due to capacitive coupling is a still unsolved problem in physical design. We describe a routing only layout solution - swizzli...
Puneet Gupta, Andrew B. Kahng
VLSID
2004
IEEE
97views VLSI» more  VLSID 2004»
16 years 7 months ago
Katha-Mala: A Voice Output Communication Aid for the Children with Severe Speech and Multiple Disorders (SSMI)
Recent developments in embedded systems technology have opened up a vast area of research and development- the development of portable and affordable assistive devices tuned to sp...
Arijit Mukhopadhyay, Saptarshi Biswas, Pratik Wora...
PERCOM
2006
ACM
16 years 6 months ago
Seamless Browsing of Visual Contents in Shared Learning Environments
This paper presents a new interaction technique for browsing large visual information bases in a collaborative environment. The ATELIER project deals with learning environments fo...
Marco Loregian, Kresimir Matkovic, Thomas Psik