Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...
Scenarios are narratives that illustrate future possibilities, such as proposed systems or plans, and help policy makers and designers choose among alternative courses of action. ...
Adaptive applications have computational workloads and communication patterns which change unpredictably at runtime, requiring dynamic load balancing to achieve scalable performan...
Hongzhang Shan, Jaswinder Pal Singh, Leonid Oliker...