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DAC
2006
ACM
16 years 8 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
16 years 1 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
GECCO
2009
Springer
193views Optimization» more  GECCO 2009»
15 years 12 months ago
Optimization of dynamic memory managers for embedded systems using grammatical evolution
New portable consumer embedded devices must execute multimedia applications (e.g., 3D games, video players and signal processing software, etc.) that demand extensive memory acces...
José L. Risco-Martín, David Atienza,...
TSE
2002
122views more  TSE 2002»
15 years 7 months ago
Virtual Benchmarking and Model Continuity in Prototyping Embedded Multiprocessor Signal Processing Systems
The complexity of hardware/software codesign of embedded real-time signal processing systems can be reduced by rapid system prototyping (RSP). However, existing RSP frameworks do n...
Randall S. Janka, Linda M. Wills, Lewis B. Baumsta...
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
15 years 5 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen