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NOCS
2010
IEEE
15 years 4 months ago
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
Tushar N. K. Jain, Paul V. Gratz, Alexander Sprint...
ISCOPE
1999
Springer
15 years 11 months ago
Using Object-Oriented Techniques for Realizing Parallel Architectural Skeletons
The concept of design patterns has recently emerged as a new paradigm in the context of object-oriented design methodology. Similar ideas are being explored in other areas of compu...
Dhrubajyoti Goswami, Ajit Singh, Bruno R. Preiss
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
16 years 19 days ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
DAC
2006
ACM
16 years 8 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
ISPD
2006
ACM
126views Hardware» more  ISPD 2006»
16 years 1 months ago
Noise driven in-package decoupling capacitor optimization for power integrity
The existing decoupling capacitance optimization approaches meet constraints on input impedance for package. In this paper, we show that using impedance as constraints leads to la...
Jun Chen, Lei He