CT The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a...
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
eriodically time-varying (LPTV) abstractions are useful for a variety of communication and computer subsystems. In this paper, we present a novel operator-based model-order reduct...
Process management and workflow systems play an important role in the composition of services in business as well as automation environments. Processes are designed using tools a...
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...