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DAC
2002
ACM
16 years 8 months ago
A general probabilistic framework for worst case timing analysis
CT The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a...
Michael Orshansky, Kurt Keutzer
DAC
2005
ACM
16 years 8 months ago
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
DAC
2005
ACM
16 years 8 months ago
Operator-based model-order reduction of linear periodically time-varying systems
eriodically time-varying (LPTV) abstractions are useful for a variety of communication and computer subsystems. In this paper, we present a novel operator-based model-order reduct...
Yayun Wan, Jaijeet S. Roychowdhury
AINA
2008
IEEE
16 years 1 months ago
WS-BPEL Process Compiler for Resource-Constrained Embedded Systems
Process management and workflow systems play an important role in the composition of services in business as well as automation environments. Processes are designed using tools a...
Hendrik Bohn, Andreas Bobek, Frank Golatowski
IPPS
2007
IEEE
16 years 1 months ago
Rethinking Automated Synthesis of MPSoC Architectures
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
Brett H. Meyer, Donald E. Thomas