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DAC
2003
ACM
16 years 8 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
BIBE
2007
IEEE
126views Bioinformatics» more  BIBE 2007»
15 years 8 months ago
FPGA Acceleration of Phylogeny Reconstruction for Whole Genome Data
In this paper we describe our design and characterization of a co-processor architecture to accelerate median-based phylogenetic reconstruction for generearrangement data. Our curr...
Jason D. Bakos, Panormitis E. Elenis, Jijun Tang
CCECE
2011
IEEE
14 years 7 months ago
Mode-matching analysis of substrate-integrated waveguide circuits
A mode-matching approach is presented for the analysis of substrate-integrated waveguide (SIW) circuits. The numerical technique takes advantage of recently developed fabrication ...
Jens Bornemann, Farzaneh Taringou
DAC
2003
ACM
16 years 5 days ago
Advanced techniques for RTL debugging
Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) so...
Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Sh...
DAC
1994
ACM
15 years 11 months ago
Error Diagnosis for Transistor-Level Verification
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...
Andreas Kuehlmann, David Ihsin Cheng, Arvind Srini...