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VLSID
2006
IEEE
71views VLSI» more  VLSID 2006»
16 years 27 days ago
Clockless Pipelining for Coarse Grain Datapaths
In this paper, we present two novel synchronization approaches to support data flow in clockless designs using single-rail encoding. Both approaches are based on self-resetting st...
Abdelhalim Alsharqawi, Abdel Ejnioui
IFE
2002
69views more  IFE 2002»
15 years 6 months ago
Generierung interaktiver Animationen von Berechnungsmodellen
In this article we introduce two new generative approaches of animated computational models. These approaches are applied in context of educational software systems for compiler de...
Stephan Diehl, Andreas Kerren
ISQED
2007
IEEE
128views Hardware» more  ISQED 2007»
16 years 1 months ago
A Model for Timing Errors in Processors with Parameter Variation
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
FDL
2005
IEEE
16 years 15 days ago
Synthesis for Unified Control- and Data-Oriented Models
In the Software/Hardware Engineering model-driven design methodology, preservation of real-time system properties can be guaranteed in the model synthesis up to a small time-deviat...
Oana Florescu, Jeroen Voeten, Henk Corporaal
DAC
2000
ACM
16 years 7 months ago
Performance analysis and optimization of latency insensitive systems
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...