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ICS
2011
Tsinghua U.
14 years 9 months ago
High performance linpack benchmark: a fault tolerant implementation without checkpointing
The probability that a failure will occur before the end of the computation increases as the number of processors used in a high performance computing application increases. For l...
Teresa Davies, Christer Karlsson, Hui Liu, Chong D...
CHI
2005
ACM
16 years 6 months ago
A study on the manipulation of 2D objects in a projector/camera-based augmented reality environment
Are the object manipulation techniques traditionally used in head?mounted displays (HMDs) applicable to augmented reality based projection systems? This paper examines the differe...
Stephen Voida, Mark Podlaseck, Rick Kjeldsen, Clau...
MOBISYS
2008
ACM
16 years 6 months ago
Improving wireless privacy with an identifier-free link layer protocol
We present the design and evaluation of an 802.11-like wireless link layer protocol that obfuscates all transmitted bits to increase privacy. This includes explicit identifiers su...
Ben Greenstein, Damon McCoy, Jeffrey Pang, Tadayos...
MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
16 years 24 days ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...
IPPS
2007
IEEE
16 years 21 days ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...