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IEEEPACT
2006
IEEE
16 years 10 days ago
Fast, automatic, procedure-level performance tuning
This paper presents an automated performance tuning solution, which partitions a program into a number of tuning sections and finds the best combination of compiler options for e...
Zhelong Pan, Rudolf Eigenmann
IEEEPACT
2006
IEEE
16 years 10 days ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
INFOCOM
2006
IEEE
16 years 10 days ago
Intelligent Distribution of Intrusion Prevention Services on Programmable Routers
— The recent surge of new viruses and host attacks in the Internet and the tremendous propagation speed of selfdistributing attacks has made network security a pressing issue. To...
Andreas Hess, Hans-Florian Geerdes, Roland Wess&au...
ISCA
2006
IEEE
187views Hardware» more  ISCA 2006»
16 years 10 days ago
A Case for MLP-Aware Cache Replacement
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
16 years 10 days ago
Silicon neurons that phase-lock
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
J. H. Wittig Jr., Kwabena Boahen
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