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IPPS
2006
IEEE
16 years 20 days ago
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
Yoshihiro Nakatani, Masanori Hariyama, Michitaka K...
DAC
2006
ACM
16 years 19 days ago
A reconfigurable design-for-debug infrastructure for SoCs
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric insert...
Miron Abramovici, Paul Bradley, Kumar N. Dwarakana...
PPSN
2004
Springer
16 years 9 hour ago
LS-CMA-ES: A Second-Order Algorithm for Covariance Matrix Adaptation
Abstract. Evolution Strategies, Evolutionary Algorithms based on Gaussian mutation and deterministic selection, are today considered the best choice as far as parameter optimizatio...
Anne Auger, Marc Schoenauer, Nicolas Vanhaecke
PPSN
2004
Springer
16 years 9 hour ago
Optimization via Parameter Mapping with Genetic Programming
Abstract. This paper describes a new approach for parameter optimization that uses a novel representation for the parameters to be optimized. By using genetic programming, the new ...
João Carlos Figueira Pujol, Riccardo Poli
IPPS
2000
IEEE
15 years 11 months ago
Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping
We consider technology mapping from factored form binary leaf-DAG to lookup tables LUTs, such as those found in eld programmable gate arrays. Polynomial time algorithms exist f...
Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi