In this paper, we argue that the address space of memory regions that participate in inter task communication is over-specified by the traditional communication models used in beh...
M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S...
Coverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools help users identify areas in the design that have not been adequat...
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...
Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Langua...
Kingshuk Karuri, Mohammad Abdullah Al Faruque, Ste...