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FPL
2003
Springer
100views Hardware» more  FPL 2003»
16 years 10 days ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
ATS
2004
IEEE
93views Hardware» more  ATS 2004»
15 years 11 months ago
Hybrid BIST Test Scheduling Based on Defect Probabilities
1 This paper describes a heuristic for system-on-chip test scheduling in an abort-on-fail context, where the test is terminated as soon as a defect is detected. We consider an hybr...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
CVPR
2000
IEEE
16 years 9 months ago
Shape and Motion Carving in 6D
The motion of a non-rigid scene over time imposes more constraints on its structure than those derived from images at a single time instant alone. An algorithm is presented for si...
Sundar Vedula, Simon Baker, Steven M. Seitz, Takeo...
BMCBI
2006
129views more  BMCBI 2006»
15 years 7 months ago
Independent Component Analysis-motivated Approach to Classificatory Decomposition of Cortical Evoked Potentials
Background: Independent Component Analysis (ICA) proves to be useful in the analysis of neural activity, as it allows for identification of distinct sources of activity. Applied t...
Tomasz G. Smolinski, Roger Buchanan, Grzegorz M. B...
RTAS
2008
IEEE
16 years 1 months ago
Schedulability Analysis of MSC-based System Models
Message Sequence Charts (MSCs) are widely used for describing interaction scenarios between the components of a distributed system. Consequently, worst-case response time estimati...
Lei Ju, Abhik Roychoudhury, Samarjit Chakraborty