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MICRO
2003
IEEE
132views Hardware» more  MICRO 2003»
15 years 12 months ago
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasa...
MICRO
2003
IEEE
135views Hardware» more  MICRO 2003»
15 years 12 months ago
Generational Cache Management of Code Traces in Dynamic Optimization Systems
A dynamic optimizer is a runtime software system that groups a program’s instruction sequences into traces, optimizes those traces, stores the optimized traces in a softwarebase...
Kim M. Hazelwood, Michael D. Smith
RTAS
2003
IEEE
15 years 12 months ago
Modular Code Generation from Hybrid Automata based on Data Dependency
Model-based automatic code generation is a process of converting abstract models into concrete implementations in the form of a program written in a high-level programming languag...
Jesung Kim, Insup Lee
SAINT
2003
IEEE
15 years 12 months ago
JGN IPv6 Network
To cope with the various problems arising from Internet protocol such as scarcity of IP addresses in the Internet and increase in the number of paths, research and development has...
Kazumasa Kobayashi, Kazuhiko Nakamura, Hisayoshi H...
VISUALIZATION
2003
IEEE
15 years 12 months ago
A Visual Exploration Process for the Analysis of Internet Routing Data
The Internet pervades many aspects of our lives and is becoming indispensable to critical functions in areas such as commerce, government, production and general information disse...
Soon Tee Teoh, Kwan-Liu Ma, Shyhtsun Felix Wu
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