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ICSE
2009
IEEE-ACM
15 years 11 months ago
Synthesis of timed behavior from scenarios in the Fujaba Real-Time Tool Suite
Based on a well-defined component architecture the tool supports the synthesis of so-called real-time statecharts from timed sequence diagrams. The two step synthesis process add...
Stefan Henkler, Joel Greenyer, Martin Hirsch, Wilh...
165
Voted
CODES
1999
IEEE
15 years 11 months ago
Scheduling with optimized communication for time-triggered embedded systems
We present an approach to process scheduling for synthesis of safety-critical distributed embedded systems. Our system model captures both the flow of data and that of control. Th...
Paul Pop, Petru Eles, Zebo Peng
163
Voted
ARCS
2006
Springer
15 years 10 months ago
A Single Issue DSP based Multi-standard Media Processor for Mobile Platforms
: This paper presents the study of modifying a legacy single-issue DSP processor to provide real-time processing capacity for emerging multimedia applications. The latest video com...
Di Wu, Tiejun Hu, Dake Liu
TACS
1991
Springer
15 years 10 months ago
On Nets, Algebras and Modularity
We aim at a unified and coherent presentation of net models for concurrency like Petri nets and dataflow networks from the perspective of modularity and substitutivity. The major ...
Alexander Moshe Rabinovich, Boris A. Trakhtenbrot
AC
2002
Springer
15 years 6 months ago
A Programming Approach to the Design of Asynchronous Logic Blocks
Abstract. Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchro...
Mark B. Josephs, Dennis P. Furey