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ISCAS
2007
IEEE
222views Hardware» more  ISCAS 2007»
16 years 17 days ago
A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters
— The complexity of Finite Impulse Response (FIR) filters is dominated by the number of adders (subtractors) used to implement the coefficient multipliers. A greedy Common Subexp...
S. Vijay, A. Prasad Vinod, Edmund Ming-Kit Lai
IPPS
1996
IEEE
15 years 10 months ago
A New Approach to Pipeline FFT Processor
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique ...
Shousheng He, Mats Torkelson
EMNLP
2008
15 years 7 months ago
Regular Expression Learning for Information Extraction
Regular expressions have served as the dominant workhorse of practical information extraction for several years. However, there has been little work on reducing the manual effort ...
Yunyao Li, Rajasekar Krishnamurthy, Sriram Raghava...
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
15 years 10 months ago
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders
—As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the co...
Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park
ISMIR
2001
Springer
117views Music» more  ISMIR 2001»
15 years 10 months ago
Score Processing For MIR
The focus of this paper is on the design and use of a music score representation. The structure of the representation is discussed and illustrated with sample algorithms, includin...
Donncha Ó. Maidín