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» Completeness Results for Memory Logics
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ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
16 years 3 months ago
Double-gate SOI devices for low-power and high-performance applications
: Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG device...
Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhop...
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
16 years 1 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
CAV
1998
Springer
175views Hardware» more  CAV 1998»
15 years 10 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
POPL
2006
ACM
16 years 6 months ago
Decidability and proof systems for language-based noninterference relations
Noninterference is the basic semantical condition used to account for confidentiality and integrity-related properties in programming languages. There appears to be an at least im...
Mads Dam
ICCAD
2006
IEEE
190views Hardware» more  ICCAD 2006»
16 years 3 months ago
Factor cuts
Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond...
Satrajit Chatterjee, Alan Mishchenko, Robert K. Br...