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VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
16 years 6 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
GLVLSI
2009
IEEE
122views VLSI» more  GLVLSI 2009»
16 years 29 days ago
Enhancing SAT-based sequential depth computation by pruning search space
The sequential depth determines the completeness of bounded model checking in design verification. Recently, a SATbased method is proposed to compute the sequential depth of a de...
Yung-Chih Chen, Chun-Yao Wang
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
16 years 20 days ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
IROS
2007
IEEE
97views Robotics» more  IROS 2007»
16 years 15 days ago
Meld: A declarative approach to programming ensembles
Abstract— This paper presents Meld, a programming language for modular robots, i.e., for independently executing robots where inter-robot communication is limited to immediate ne...
Michael P. Ashley-Rollman, Seth Copen Goldstein, P...
ESWS
2005
Springer
15 years 11 months ago
DRAGO: Distributed Reasoning Architecture for the Semantic Web
The paper addresses the problem of reasoning with multiple ontologies interrelated with semantic mappings. This problem is becoming more and more relevant due to the necessity of b...
Luciano Serafini, Andrei Tamilin