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» Completeness Results for Memory Logics
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RTSS
2009
IEEE
16 years 1 months ago
Multiprocessor Extensions to Real-Time Calculus
Abstract—Many embedded platforms consist of a heterogeneous collection of processing elements, memory modules, and communication subsystems. These components often implement diff...
Hennadiy Leontyev, Samarjit Chakraborty, James H. ...
FMCAD
2009
Springer
16 years 26 days ago
Scaling VLSI design debugging with interpolation
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
Brian Keng, Andreas G. Veneris
SOUPS
2009
ACM
16 years 24 days ago
Graphical passwords as browser extension: implementation and usability study
Abstract: Today, most Internet applications still establish user authentication with traditional text based passwords. Designing a secure as well as a user-friendly password-based ...
Kemal Bicakci, Mustafa Yuceel, Burak Erdeniz, Haka...
ARCS
2010
Springer
16 years 24 days ago
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
Jörg Mische, Irakli Guliashvili, Sascha Uhrig...
CGO
2007
IEEE
16 years 19 days ago
On the Complexity of Register Coalescing
Memory transfers are becoming more important to optimize, for both performance and power consumption. With this goal in mind, new register allocation schemes are developed, which ...
Florent Bouchez, Alain Darte, Fabrice Rastello