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» Compiling SA-C Programs to FPGAs: Performance Results
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ML
2002
ACM
114views Machine Learning» more  ML 2002»
15 years 5 months ago
Building a Basic Block Instruction Scheduler with Reinforcement Learning and Rollouts
The execution order of a block of computer instructions on a pipelined machine can make a difference in running time by a factor of two or more. Compilers use heuristic schedulers...
Amy McGovern, J. Eliot B. Moss, Andrew G. Barto
MICRO
1998
IEEE
98views Hardware» more  MICRO 1998»
15 years 10 months ago
Task Selection for a Multiscalar Processor
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
T. N. Vijaykumar, Gurindar S. Sohi
IEEEPACT
2005
IEEE
15 years 11 months ago
Instruction Based Memory Distance Analysis and its Application
Feedback-directed Optimization has become an increasingly important tool in designing and building optimizing compilers as itprovides a means to analyze complexprogram behavior th...
Changpeng Fang, Steve Carr, Soner Önder, Zhen...
FPL
2010
Springer
188views Hardware» more  FPL 2010»
15 years 4 months ago
SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing
We demonstrate how Field Programmable Gate Arrays (FPGAs) may be used to address the computing challenges associated with assembling genome sequences from recent ultra-high-through...
Kristian Stevens, Henry Chen, Terry Filiba, Peter ...
IPSN
2007
Springer
16 years 4 days ago
The regiment macroprogramming system
The development of high-level programming environments is essential if wireless sensor networks are to be accessible to nonexperts. In this paper, we present the Regiment system, ...
Ryan Newton, Greg Morrisett, Matt Welsh