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DATE
2003
IEEE
97views Hardware» more  DATE 2003»
15 years 11 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
CLEF
2003
Springer
15 years 11 months ago
Regular Sound Changes for Cross-Language Information Retrieval
The aim of this project is the automatic conversion of query terms in one language into their equivalents in a second, historically related, language, so that documents in the sec...
Michael P. Oakes, Souvik Banerjee
ISHPC
2003
Springer
15 years 11 months ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos
ICICS
2001
Springer
15 years 11 months ago
Enforcing Obligation with Security Monitors
With the ubiquitous deployment of large scale networks more and more complex human interactions are supported by computer applications. This poses new challenges on the expressive...
Carlos Ribeiro, Andre Zuquete, Paulo Ferreira
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
15 years 10 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis