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» Comparing the Optimal Performance of Parallel Architectures
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ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 12 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
CLUSTER
2008
IEEE
16 years 23 days ago
A multicore-enabled multirail communication engine
—The current trend in clusters architecture leads toward a massive use of multicore chips. This hardware evolution raises bottleneck issues at the network interface level. The us...
Elisabeth Brunet, François Trahay, Alexandr...
ISPASS
2007
IEEE
16 years 17 days ago
Cross Binary Simulation Points
Architectures are usually compared by running the same workload on each architecture and comparing performance. When a single compiled binary of a program is executed on many diff...
Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jal...
ICS
2010
Tsinghua U.
15 years 8 months ago
Speeding up Nek5000 with autotuning and specialization
Autotuning technology has emerged recently as a systematic process for evaluating alternative implementations of a computation, in order to select the best-performing solution for...
Jaewook Shin, Mary W. Hall, Jacqueline Chame, Chun...
CF
2008
ACM
15 years 8 months ago
Fpga-based prototype of a pram-on-chip processor
PRAM (Parallel Random Access Model) has been widely regarded a desirable parallel machine model for many years, but it is also believed to be "impossible in reality." As...
Xingzhi Wen, Uzi Vishkin