1461 search results - page 159 / 293 » Comparing the Optimal Performance of Parallel Architectures |
160
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IEEEPACT
2006
IEEE
16 years 7 days ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
160
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FPL
2009
Springer
15 years 10 months ago
2009
Springer
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
162
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ASAP
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper, we present a modular co-synthesis framework called CHARMED that solves the problem of hardware-software co-synthesis of periodic, multi-mode, distributed, embedded ...
165
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TCOM
2010
15 years 28 days ago
2010
This paper proposes a capacity-approaching, yet simple scheme for multi-input multiple-output (MIMO) channels. The proposed scheme is based on a concatenation of a mixture of short...
174
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IWMM
2009
Springer
16 years 23 days ago
2009
Springer
In this paper, we investigate the effects of using three different nursery sizing policies on overall and garbage collection performances. As part of our investigation, we modify ...