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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 9 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie
AI
2010
Springer
15 years 7 months ago
Implementing logical connectives in constraint programming
Combining constraints using logical connectives such as disjunction is ubiquitous in constraint programming, because it adds considerable expressive power to a constraint language...
Christopher Jefferson, Neil C. A. Moore, Peter Nig...
PAMI
2002
150views more  PAMI 2002»
15 years 7 months ago
Object Tracking with Bayesian Estimation of Dynamic Layer Representations
Decomposing video frames into coherent two-dimensional motion layers is a powerful method for representing videos. Such a representation provides an intermediate description that e...
Hai Tao, Harpreet S. Sawhney, Rakesh Kumar
TVLSI
2010
15 years 2 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
DAC
2007
ACM
16 years 8 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram