20197 search results - page 707 / 4040 » Comparing Computational Power |
172
Voted
ASYNC
2005
IEEE
16 years 1 months ago
2005
IEEE
We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Selftimed circuitry both generates and distributes a clock signal, wh...
143
click to vote
ISCAS
2005
IEEE
16 years 1 months ago
2005
IEEE
In this paper, a framework of designing a low-error and power-efficient two’s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit produ...
189
click to vote
SBCCI
2003
ACM
16 years 21 days ago
2003
ACM
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
148
click to vote
ASPDAC
1998
ACM
15 years 11 months ago
1998
ACM
-- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET fl...
195
click to vote
TVLSI
2002
15 years 7 months ago
2002
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...