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BMCBI
2010
218views more  BMCBI 2010»
15 years 7 months ago
Fast multi-core based multimodal registration of 2D cross-sections and 3D datasets
Background: Solving bioinformatics tasks often requires extensive computational power. Recent trends in processor architecture combine multiple cores into a single chip to improve...
Michael Scharfe, Rainer Pielot, Falk Schreiber
CARDIS
2010
Springer
168views Hardware» more  CARDIS 2010»
16 years 2 months ago
Secure Delegation of Elliptic-Curve Pairing
In this paper we describe a simple protocol for secure delegation of the elliptic-curve pairing. A computationally limited device (typically a smart-card) will delegate the computa...
Benoît Chevallier-Mames, Jean-Sébasti...
IPPS
2006
IEEE
16 years 1 months ago
Online strategies for high-performance power-aware thread execution on emerging multiprocessors
Granularity control is an effective means for trading power consumption with performance on dense shared memory multiprocessors, such as multi-SMT and multi-CMP systems. In this p...
Matthew Curtis-Maury, James Dzierwa, Christos D. A...
SAC
2010
ACM
15 years 9 months ago
Energy-efficient scheduling on homogeneous multiprocessor platforms
Low-power and energy-efficient system implementations have become very important design issues to extend operation duration or cut power bills. To balance the energy consumption r...
Jian-Jia Chen, Lothar Thiele
SAC
2008
ACM
15 years 7 months ago
Power-efficient and scalable load/store queue design via address compression
This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fullyas...
Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen