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DAC
2006
ACM
16 years 8 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong
DAC
2006
ACM
16 years 8 months ago
Gate sizing: finFETs vs 32nm bulk MOSFETs
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
Brian Swahn, Soha Hassoun
ISBI
2008
IEEE
16 years 8 months ago
Pathological image segmentation for neuroblastoma using the GPU
We present a novel use of GPUs (Graphics Processing Units) for the analysis of histopathologicalimages of neuroblastoma, a childhood cancer. Thanks to the advent of modern microsc...
Antonio Ruiz, Jun Kong, Manuel Ujaldon, Kim L. Boy...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
16 years 7 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
16 years 7 months ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong