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CASES
2004
ACM
16 years 12 days ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
DAC
2000
ACM
16 years 8 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
16 years 3 months ago
Making register file resistant to power analysis attacks
— Power analysis attacks are a type of side-channel attacks that exploits the power consumption of computing devices to retrieve secret information. They are very effective in br...
Shuo Wang, Fan Zhang, Jianwei Dai, Lei Wang, Zhiji...
MSS
2005
IEEE
62views Hardware» more  MSS 2005»
16 years 16 days ago
Predictive Reduction of Power and Latency (PuRPLe)
Increasing efforts have been aimed towards the management of power as a critical system resource, and the disk can consume approximately a third of the power required for a typica...
Matthew Craven, Ahmed Amer
INFOCOM
2008
IEEE
16 years 1 months ago
Power-Adjusted Random Access to a Wireless Channel
—The operation of widely-deployed random access to wireless networks is based on limited information on the result of each access attempt. When making a random access attempt, us...
Young-June Choi, Kang G. Shin