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EUC
2004
Springer
16 years 10 days ago
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...
Seiichiro Fujii, Toshinori Sato
DATE
2010
IEEE
129views Hardware» more  DATE 2010»
16 years 1 days ago
A power optimization method for CMOS Op-Amps using sub-space based geometric programming
—— A new sub-space max-monomial modeling scheme for CMOS transistors in sub-micron technologies is proposed to improve the modeling accuracy. Major electrical parameters of CMOS...
Wei Gao, Richard Hornsey
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
15 years 8 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
DAGSTUHL
2006
15 years 8 months ago
Physical 2D Morphware and Power Reduction Methods for Everyone
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the p...
Jürgen Becker, Michael Hübner, Katarina ...
CORR
2007
Springer
111views Education» more  CORR 2007»
15 years 6 months ago
A New Perspective on Multi-user Power Control Games in Interference Channels
This paper considers the problem of how to allocate power among competing users sharing a frequency-selective interference channel. We model the interaction between these selfish ...
Yi Su, Mihaela van der Schaar