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DAC
2007
ACM
16 years 8 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
1999
ACM
16 years 8 months ago
Memory Exploration for Low Power, Embedded Systems
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
Wen-Tsong Shiue, Chaitali Chakrabarti
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
16 years 7 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
VLSID
2002
IEEE
149views VLSI» more  VLSID 2002»
16 years 7 months ago
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
Yunsi Fei, Niraj K. Jha
ASPDAC
2009
ACM
143views Hardware» more  ASPDAC 2009»
16 years 1 months ago
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
In this paper, we present a novel statistical full-chip leakage power analysis method. The new method can provide a general framework to derive the full-chip leakage current or po...
Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai...