Sciweavers

20197 search results - page 495 / 4040
» Comparing Computational Power
Sort
View
DAC
2005
ACM
16 years 8 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
DAC
2006
ACM
16 years 8 months ago
Leakage power reduction of embedded memories on FPGAs through location assignment
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
Yan Meng, Timothy Sherwood, Ryan Kastner
VLSID
2006
IEEE
134views VLSI» more  VLSID 2006»
16 years 7 months ago
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective
This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and dis...
Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
VLSID
2002
IEEE
138views VLSI» more  VLSID 2002»
16 years 7 months ago
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
Haris Lekatsas, Jörg Henkel
ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
16 years 3 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton