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HPCA
2003
IEEE
16 years 7 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
RTSS
2009
IEEE
16 years 1 months ago
Adaptive Dynamic Power Management for Hard Real-Time Systems
Abstract—Power dissipation has constrained the performance boosting of modern computer systems in the past decade. Dynamic power management has been widely applied to change the ...
Kai Huang, Luca Santinelli, Jian-Jia Chen, Lothar ...
AINA
2007
IEEE
16 years 1 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
BROADNETS
2007
IEEE
16 years 1 months ago
Reconsidering power management
— Power-management approaches have been widely studied in an attempt to conserve idling energy by allowing nodes to switch to a low-power sleep mode. However, due to the inherent...
Cigdem Sengul, Albert F. Harris III, Robin Kravets
IPPS
2005
IEEE
16 years 12 days ago
Toward an Evaluation Infrastructure for Power and Energy Optimizations
Execution-driven simulators are often used for power/energy and performance evaluation. Simulators can provide semantic details but they provide insufficient speed and accuracy f...
Chunling Hu, Daniel A. Jiménez, Ulrich Krem...