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CF
2008
ACM
15 years 8 months ago
Low power microarchitecture with instruction reuse
Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power...
Frederico Pratas, Georgi Gaydadjiev, Mladen Bereko...
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
15 years 4 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
Andrew B. Kahng, Bill Lin, Kambiz Samadi
WIOPT
2010
IEEE
15 years 4 months ago
Iterative power and subcarrier allocation for maximizing WSMR in cellular OFDMA systems
We consider the resource allocation (RA) problem of maximizing the weighted sum of the minimal user rates (WSMR) of coordinated cells subject to a total power constraint at each ba...
Tao Wang, Luc Vandendorpe
ICCAD
2002
IEEE
143views Hardware» more  ICCAD 2002»
16 years 3 months ago
A Markov chain sequence generator for power macromodeling
In macromodeling-based power estimation, circuit macromodels are created from simulations of synthetic input vector sequences. Fast generation of these sequences with all possible...
Xun Liu, Marios C. Papaefthymiou
DATE
2008
IEEE
170views Hardware» more  DATE 2008»
16 years 1 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy