Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
Abstract--In this paper we develop a new analytical methodology for the evaluation of the outage probability of cooperative decode-and-forward (DF) automatic-repeat-request (ARQ) r...
Sangkook Lee, Weifeng Su, Stella N. Batalama, John...
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
—Parallelism has often been used to improve the reliability and efficiency of a variety of different engineering systems. In this paper, we quantify the efficiency of paralleli...
Jian Tan, Wei Wei, Bo Jiang, Ness Shroff, Donald F...