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185
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ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 11 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
167
Voted
JETC
2008
127views more  JETC 2008»
15 years 5 months ago
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
Yong Zhan, Sachin S. Sapatnekar
TWC
2010
15 years 1 months ago
Cooperative Decode-and-Forward ARQ Relaying: Performance Analysis and Power Optimization
Abstract--In this paper we develop a new analytical methodology for the evaluation of the outage probability of cooperative decode-and-forward (DF) automatic-repeat-request (ARQ) r...
Sangkook Lee, Weifeng Su, Stella N. Batalama, John...
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
16 years 1 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...
180
Voted
SIGMETRICS
2010
ACM
187views Hardware» more  SIGMETRICS 2010»
15 years 11 months ago
Can multipath mitigate power law delays?: effects of parallelism on tail performance
—Parallelism has often been used to improve the reliability and efficiency of a variety of different engineering systems. In this paper, we quantify the efficiency of paralleli...
Jian Tan, Wei Wei, Bo Jiang, Ness Shroff, Donald F...