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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
15 years 6 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
PIMRC
2010
IEEE
15 years 4 months ago
Power control versus multiuser detection based cross-layer design in wireless ad hoc networks
Abstract--In wireless ad hoc networks, multiple access interference is the limiting factor for the overall system performance. The lack of any central control unit necessitates a c...
Ulrike Korger, Christian Hartmann, Katsutoshi Kusu...
WSC
2008
15 years 9 months ago
Better than a petaflop: The power of efficient experimental design
Recent advances in high-performance computing have pushed computational capabilities to a petaflop (a thousand trillion operations per second) in a single computing cluster. This ...
Susan M. Sanchez
EOR
2011
140views more  EOR 2011»
15 years 1 months ago
Power indices of simple games and vector-weighted majority games by means of binary decision diagrams
A simple game is a pair consisting of a finite set N of players and a set W ⊆ 2N of winning coalitions. (Vector-)weighted majority games ((V)WMG) are a special case of simple ga...
Stefan Bolus