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ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
16 years 3 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 22 days ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
168
Voted
ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
16 years 21 days ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
15 years 11 months ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
BMCBI
2008
179views more  BMCBI 2008»
15 years 6 months ago
Improving the power for detecting overlapping genes from multiple DNA microarray-derived gene lists
Background: In DNA microarray gene expression profiling studies, a fundamental task is to extract statistically significant genes that meet certain research hypothesis. Currently,...
Xutao Deng, Jun Xu, Charles Wang