20197 search results - page 329 / 4040 » Comparing Computational Power |
153
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IPPS
2000
IEEE
15 years 11 months ago
2000
IEEE
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
177
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DAC
1994
ACM
15 years 10 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
145
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APPT
2009
Springer
15 years 10 months ago
2009
Springer
Abstract. In many-core CMP architectures, the cache coherence protocol is a key component since it can add requirements of area and power consumption to the final design and, there...
181
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CASES
2008
ACM
15 years 8 months ago
2008
ACM
Power, energy, and thermal concerns have constrained embedded systems designs. Computing capability and storage density have increased dramatically, enabling the emergence of hand...
157
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DPHOTO
2010
15 years 8 months ago
2010
We describe the procedure to evaluate the image quality of a camera in terms of texture preservation. We use a stochastic model coming from stochastic geometry, and known as the d...