20197 search results - page 290 / 4040 » Comparing Computational Power |
138
click to vote
ISCA
2006
IEEE
16 years 20 days ago
2006
IEEE
One of the key challenges for high-density servers (e.g., blades) is the increased costs in addressing the power and heat density associated with compaction. Prior approaches have...
157
click to vote
ASPDAC
2006
ACM
16 years 18 days ago
2006
ACM
Extensive research has proposed the use of multiple on-die power supplies (VDD) for reducing power consumption in CMOS circuits. We present a detailed study and design techniques ...
221
click to vote
CODES
2003
IEEE
15 years 12 months ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
159
click to vote
ICCAD
1997
IEEE
15 years 11 months ago
1997
IEEE
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
159
click to vote
ICCD
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...