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FCT
1999
Springer
15 years 11 months ago
Iterative Arrays with a Wee Bit Alternation
Abstract. An iterative array is a line of interconnected interacting finite automata. One distinguished automaton, the communication cell, is connected to the outside world and fe...
Thomas Buchholz, Andreas Klein, Martin Kutrib
DAC
1994
ACM
15 years 10 months ago
A Modular Partitioning Approach for Asynchronous Circuit Synthesis
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...
Ruchir Puri, Jun Gu
ICIP
2009
IEEE
16 years 7 months ago
Optimal Power Allocation For Minimizing Visual Distortion Over Mimo Communication Systems
A recent dynamic increase in demand for wireless multimedia services has greatly accelerated the research on cross layer optimization techniques for transmitting multimedia data o...
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
16 years 3 months ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
ASPDAC
2009
ACM
104views Hardware» more  ASPDAC 2009»
16 years 1 months ago
Addressing thermal and power delivery bottlenecks in 3D circuits
— The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footpr...
Sachin S. Sapatnekar