20197 search results - page 259 / 4040 » Comparing Computational Power |
151
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ISLPED
1997
ACM
15 years 10 months ago
1997
ACM
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
116
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JSAC
2006
15 years 6 months ago
2006
This manuscript introduces a mathematically tractable and accurate model of narrowband power line noise based on experimental measurements. In this paper, the noise is expressed as...
145
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TIT
2002
15 years 6 months ago
2002
This paper extends our earlier results. We assume that the receiver has the capability of capturing multiple packets so long as the signal-to-interference-plus-noise ratio (SINR) o...
192
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ISQED
2010
IEEE
15 years 4 months ago
2010
IEEE
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
143
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ESSCIRC
2011
14 years 6 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...