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ISCAS
2003
IEEE
101views Hardware» more  ISCAS 2003»
15 years 11 months ago
A 5th order Volterra study of a 30W LDMOS power amplifier
A 30 W LDMOS is modeled using a 5th order polynomial model. The polynomial model is compared to the largesignal MET model using harmonic balance, and as the results agreed very we...
Antti Heiskanen, Janne Aikio, Timo Rahkonen
HICSS
2008
IEEE
156views Biometrics» more  HICSS 2008»
16 years 1 months ago
A Centrality Measure for Electrical Networks
—We derive a measure of “electrical centrality” for AC power networks, which describes the structure of the network as a function of its electrical topology rather than its p...
Paul Hines, Seth Blumsack
ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
16 years 24 days ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
ICICS
2009
Springer
16 years 1 months ago
GUC-Secure Join Operator in Distributed Relational Database
Privacy-preserving SQL computation in distributed relational database is one of important applications of secure multiparty computation. In contrast with comparatively more works o...
Yuan Tian, Hao Zhang
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
15 years 4 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi